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8018P–AVR–08/10
ATmega169P
16.4
Register Description
16.4.1
GTCCR – General Timer/Counter Control Register
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,
and the Timer/Counters start counting simultaneously.
Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
Bit
7
6
5
4
3
2
1
0
0x23 (0x43)
TSM
–
PSR2
PSR10
GTCCR
Read/Write
R/W
R
R/W
Initial Value
0
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相关PDF资料
2-1546217-0 TERM BLK RCPT 20POS SIDE 5.08MM
1-1546217-9 TERM BLK RCPT 19POS SIDE 5.08MM
1-1546217-8 TERM BLK RCPT 18POS SIDE 5.08MM
1-1546217-7 TERM BLK RCPT 17POS SIDE 5.08MM
1-1546217-6 TERM BLK RCPT 16POS SIDE 5.08MM
1-1546217-5 TERM BLK RCPT 15POS SIDE 5.08MM
1-1546217-4 TERM BLK RCPT 14POS SIDE 5.08MM
1-1546217-3 TERM BLK RCPT 13POS SIDE 5.08MM
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